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<!-- <p>200mm</p>
<li>A size of silicon wafer approximately 8 inches in diameter. Also used to refer to a tool designed to process wafers of this size.</li>
<p>300mm</p>
<li>A size of silicon wafer approximately 12 inches in diameter. Also used to refer to a tool designed to process wafers of this size.</li>
<p>4K RESOLUTION</p>
<li>An alternative term for the UHD digital video format.</li> -->
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<!-- <li>
<h5 id="A">A</h5>
<p>ABATEMENT</p>
<li>A process where toxic or other hazardous substances are removed from a liquid or gas. Examples include removing copper particles from CMP slurry or converting liquid or gaseous toxic effluents into safe forms for disposal.</li>
<p>ACCELERATOR</p>
<li>In ion implantation, a device used to increase the energy of an atom or molecule. (See Extraction Electrode).</li>
<p>ACCEPTOR</p>
<li>An impurity in a semiconductor that accepts electrons. Boron is the primary acceptor used to dope silicon in the ion implantation process.</li>
<p>ACCUMULATOR</p>
<li>A storage unit used to temporarily store work-in-progress in a manufacturing line.</li>
<p>ACTIVE MATRIX OLED DISPLAY (AMOLED)</p>
<li>A type of display that uses an array of electroluminescent OLED pixels controlled by thin-film transistors.</li>
</li>
<li>
<h5 id="B">B</h5>
<p>BACK-SCATTERED ELECTRON</p>
<li>A type of electron that results from primary electrons hitting a sample in eBeam imaging. Back-scattered electrons are useful in imaging through multiple layers of materials and high-aspect ratio (HAR) structures.</li>
<p>BACK CONTACT</p>
<li>A metallic layer that covers the entire back surface of a solar PV cell and acts as a conductor.</li>
<li>Also used to refer to advanced cell designs such as EWT where both terminals of the cell are located on the back side of the wafer, thus increasing the light-gathering area of the cell and hence improving conversion efficiency.</li>
<p>BACK GLASS</p>
<li>The bottom layer of a thin film solar module, which provides rigidity and electrical insulation. Current is extracted from the module through the junction box that is attached to the circuit through a hole in the back glass.</li>
<p>BACKPLANE</p>
<li>In TFT-LCD manufacturing, the backplane is the array of thin-film transistors that control the light output of each pixel on the display.</li>
<li>There are three major backplane technologies described by the material used to make the transistor channel: amorphous silicon, metal oxide and low-temperature polysilicon.</li>
<p>BAKEOUT</p>
<li>The technique of accelerating the degassing of surfaces of a vacuum system or a component by heating during the vacuum pumping process. Used to reduce the time taken to reach UHV pressures.</li>
</li>
<li>
<h5 id="C">C</h5>
<p>CAPACITANCE</p>
<li>The degree to which a material can store an electrical charge.</li>
<p>CAPACITOR</p>
<li>An electrical component used to temporarily store a charge. It consists of two conducting surfaces separated by a non-conducting dielectric.</li>
<p>CARRIER</p>
<li>An electron or hole that carries electric charge through a conducting or semiconducting material.</li>
<p>CARRIER MOBILITY</p>
<li>A measure, typically specified in cm2/V·s, of how rapidly a charge carrier (an electron or hole) can move through a semiconductor in response to an applied electric field. The conductivity of a material is proportional to mobility multiplied by the concentration of carriers. High mobility is highly desirable in semiconductor devices because it leads to higher device performance through faster transistor switching.</li>
<p>CASSETTE</p>
<li>A metal or plastic open container used for transporting wafers (usually 25) to and from a tool. Cassettes protect wafers from damage that could be caused by direct handling</li>
<p>CD-SEM (CRITICAL DIMENSION SCANNING ELECTRON MICROSCOPE)</p>
<li>A type of scanning electron microscope used to measure critical dimensions.</li>
<p>CD-TE</p>
<li>A category of thin-film solar cells that uses a cadmium-tellurium compound as the light-converting active layer.</li>
<p>CDU (CRITICAL DIMENSION UNIFORMITY)</p>
<li>a parameter used in etch to describe precision of the etch process. CDU is defined as the variation of the size of a repeating feature from its nominal value (CD) measured at several points across the substrate.</li>
<p>CFD</p>
<li>Computational Fluid Dynamics, a branch of fluid mechanics that uses numerical methods and algorithms to solve and analyze problems that involve fluid flows.</li>
</li>
<li>
<h5 id="D">D</h5>
<p>DAMAGE ENGINEERING</p>
<li>A class of techniques using in ion implantation used to control the electrical characteristics of a semiconductor device by intentionally disrupting the silicon crystal structure.</li>
<p>DAMASCENE</p>
<li>A means of creating copper metal interconnects by over-filling trenches in the interlayer dielectric using ECD then using CMP to remove the excess copper.
DARC (DIELECTRIC ANTI-REFLECTIVE COATING)</li>
<p>DARKFIELD INSPECTION</p>
<li>A defect inspection technique that uses detectors that collect scattered light to make a defect appear bright against a dark background. Typically used to find particles on wafers during interconnect fabrication. Compare with brightfield inspection.</li>
<p>DEEP ULTRAVIOLET (DUV)</p>
<li>The portion of the ultraviolet light spectrum with wavelengths below 300nm.</li>
<p>DEFECT</p>
<li>Any foreign substance on the wafer (physical defect) or parts of a pattern that are missing or do not belong (pattern defect).</li>
<p>DEFECT INSPECTION</p>
<li>A process where defects are located on a patterned wafer. A list of defect locations is created and passed to a DR-SEM for review and classification.</li>
<p>DEFECT REVIEW SCANNING ELECTRON MICROSCOPE (DR-SEM)</p>
<li>A type of scanning electron microscope used to classify defect types during the wafer manufacturing process and determine whether these defects will affect chip yields.</li>
<p>DEEP ULTRAVIOLET (DUV)</p>
<li>The portion of the ultraviolet light spectrum with wavelengths below 300nm.</li>
<p>DEFECT</p>
<li>Any foreign substance on the wafer (physical defect) or parts of a pattern that are missing or do not belong (pattern defect).</li>
</li>
<li>
<h5 id="E">E</h5>
<p>eBEAM (ELECTRON BEAM)</p>
<li>An imaging technology, where primary electrons are fired at a sample in order to gather information such as secondary electrons or backscattered electrons and produce an image.</li>
<p>ECA (ELECTRICALLY CONDUCTIVE ADHESIVE)</p>
<li>Composite material comprising a resin component enabling adhesion and conductive particles suspended into it enabling conductivity. When the resin component is cured, the conductive particles get in contact to each other enabling the electrical conductivity.</li>
<p>EDGE PLACEMENT ERROR</p>
<li>The difference between the intended and the printed features of an IC layout. In metrology, it is a metric based on extreme value statistics that combines all the variations both in CD and Overlay domains.</li>
<p>EFFICIENCY</p>
<li>In solar PV technology, the fraction of incident solar energy that is converted to electrical energy.</li>
<p>ELECTRO-MIGRATION</p>
<li>Movement of material caused by ion motion in a conductor that arises from the momentum transfer between conducting electrons and diffusing metal atoms.</li>
<p>ELECTROCHEMICAL DEPOSITION (ECD)</p>
<li>A deposition process in which metals are removed from a chemical solution and deposited on a charged surface. Also referred to as electrochemical plating, electroplating, or electrodeposition.</li>
<p>ELECTRODE</p>
<li>An electrical conductor used to contact a nonmetallic part of a circuit (e.g., a semiconductor).</li>
<p>ELECTROLYTIC</p>
<li>Performed by means of electrolysis, which is the process of separating a liquid into its different chemical parts by passing an electric current through it.</li>
<p>ELECTROMAGNETIC INTERFERENCE (EMI)</p>
<li>The effect resulting from multiple sources emitting electromagnetic waves at the same frequency spectrum.</li>
</li>
<li>
<h5 id="F">F</h5>
<p>FAB</p>
<li>Common name for a semiconductor fabrication plant, a factory used to manufacture integrated circuits.</li>
<p>FAN-OUT</p>
<li>Also known as Embedded Wafer-Level Ball Grid Array. A chip packaging scheme in which the package is not created on a silicon wafer, but on an artificial wafer made of molding material (e.g., epoxy). The distance between chips is typically larger than on a silicon wafer. Interconnects are created around the chips and electrical connections are made from the chip pads to the interconnects. Any number of additional interconnects can be created on the package in an arbitrary distance (fan-out design), making this scheme ideal for space-sensitive applications in which the chip area would be insufficient to place the required number of interconnects at a suitable distance.</li>
<p>FDC (FAULT DETECTION AND CLASSIFICATION)</p>
<li>An APC technique that uses process state models to deduce the occurrence and location of a fault condition and diagnose the cause of the fault.</li>
<p>FEOL (FRONT-END OF LINE)</p>
<li>The first portion of integrated circuit fabrication including transistor fabrication. FEOL generally covers everything up to (but not including) the deposition of contacts and metal interconnect layers. The term front end is sometimes used to refer the entire process to completed wafers.</li>
<p>FET (FIELD EFFECT TRANSISTOR)</p>
<li>A type of transistor that relies on an electric field to control the flow of charge carriers in a semiconductor material.</li>
<p>FI (FACTORY INTERFACE)</p>
<li>An ultra-clean enclosure mounted to the front of a semiconductor processing system that transfers wafers to and from the cleanroom environment and the interior of the system.</li>
<p>FIELD</p>
<li>A term used in deposition applications to describe the top surface of a wafer as distinct from the surfaces of circuit features such as trenches and vias that are lower than the top surface.</li>
<p>FINFET</p>
<li>A FinFET is a type of FET in which the conducting channel is surrounded on three sides by a thin silicon "fin" which forms the gate of the transistor. Although technically the term only refers to a design with two gates, the term is often used to describe any multi-gate transistor architecture, regardless of the number of gates.</li>
<p>FLASH MEMORY</p>
<li>A type of non-volatile storage technology that requires no power to retain data, unlike DRAM. The name "flash" comes from the fact that the memory is erased and programmed in large blocks, from hundreds to thousands of bits at a time. This inability to address individual bits makes it too slow for direct connection to a microprocessor, but the mechanical robustness and low cost of flash makes it ideal for mass storage in mobile devices.</li>
</li>
<li>
<h5 id="G">G</h5>
<p>FAB</p>
<li>Common name for a semiconductor fabrication plant, a factory used to manufacture integrated circuits.</li>
<p>FAN-OUT</p>
<li>Also known as Embedded Wafer-Level Ball Grid Array. A chip packaging scheme in which the package is not created on a silicon wafer, but on an artificial wafer made of molding material (e.g., epoxy). The distance between chips is typically larger than on a silicon wafer. Interconnects are created around the chips and electrical connections are made from the chip pads to the interconnects. Any number of additional interconnects can be created on the package in an arbitrary distance (fan-out design), making this scheme ideal for space-sensitive applications in which the chip area would be insufficient to place the required number of interconnects at a suitable distance.</li>
<p>FDC (FAULT DETECTION AND CLASSIFICATION)</p>
<li>An APC technique that uses process state models to deduce the occurrence and location of a fault condition and diagnose the cause of the fault.</li>
<p>FEOL (FRONT-END OF LINE)</p>
<li>The first portion of integrated circuit fabrication including transistor fabrication. FEOL generally covers everything up to (but not including) the deposition of contacts and metal interconnect layers. The term front end is sometimes used to refer the entire process to completed wafers.</li>
<p>FET (FIELD EFFECT TRANSISTOR)</p>
<li>A type of transistor that relies on an electric field to control the flow of charge carriers in a semiconductor material.</li>
<p>FI (FACTORY INTERFACE)</p>
<li>An ultra-clean enclosure mounted to the front of a semiconductor processing system that transfers wafers to and from the cleanroom environment and the interior of the system.</li>
<p>FIELD</p>
<li>A term used in deposition applications to describe the top surface of a wafer as distinct from the surfaces of circuit features such as trenches and vias that are lower than the top surface.</li>
<p>FINFET</p>
<li>A FinFET is a type of FET in which the conducting channel is surrounded on three sides by a thin silicon "fin" which forms the gate of the transistor. Although technically the term only refers to a design with two gates, the term is often used to describe any multi-gate transistor architecture, regardless of the number of gates.</li>
<p>FLASH MEMORY</p>
<li>A type of non-volatile storage technology that requires no power to retain data, unlike DRAM. The name "flash" comes from the fact that the memory is erased and programmed in large blocks, from hundreds to thousands of bits at a time. This inability to address individual bits makes it too slow for direct connection to a microprocessor, but the mechanical robustness and low cost of flash makes it ideal for mass storage in mobile devices.</li>
</li>
<li>
<h5 id="H">H</h5>
<p>FAB</p>
<li>Common name for a semiconductor fabrication plant, a factory used to manufacture integrated circuits.</li>
<p>FAN-OUT</p>
<li>Also known as Embedded Wafer-Level Ball Grid Array. A chip packaging scheme in which the package is not created on a silicon wafer, but on an artificial wafer made of molding material (e.g., epoxy). The distance between chips is typically larger than on a silicon wafer. Interconnects are created around the chips and electrical connections are made from the chip pads to the interconnects. Any number of additional interconnects can be created on the package in an arbitrary distance (fan-out design), making this scheme ideal for space-sensitive applications in which the chip area would be insufficient to place the required number of interconnects at a suitable distance.</li>
<p>FDC (FAULT DETECTION AND CLASSIFICATION)</p>
<li>An APC technique that uses process state models to deduce the occurrence and location of a fault condition and diagnose the cause of the fault.</li>
<p>FEOL (FRONT-END OF LINE)</p>
<li>The first portion of integrated circuit fabrication including transistor fabrication. FEOL generally covers everything up to (but not including) the deposition of contacts and metal interconnect layers. The term front end is sometimes used to refer the entire process to completed wafers.</li>
<p>FET (FIELD EFFECT TRANSISTOR)</p>
<li>A type of transistor that relies on an electric field to control the flow of charge carriers in a semiconductor material.</li>
<p>FI (FACTORY INTERFACE)</p>
<li>An ultra-clean enclosure mounted to the front of a semiconductor processing system that transfers wafers to and from the cleanroom environment and the interior of the system.</li>
<p>FIELD</p>
<li>A term used in deposition applications to describe the top surface of a wafer as distinct from the surfaces of circuit features such as trenches and vias that are lower than the top surface.</li>
<p>FINFET</p>
<li>A FinFET is a type of FET in which the conducting channel is surrounded on three sides by a thin silicon "fin" which forms the gate of the transistor. Although technically the term only refers to a design with two gates, the term is often used to describe any multi-gate transistor architecture, regardless of the number of gates.</li>
<p>FLASH MEMORY</p>
<li>A type of non-volatile storage technology that requires no power to retain data, unlike DRAM. The name "flash" comes from the fact that the memory is erased and programmed in large blocks, from hundreds to thousands of bits at a time. This inability to address individual bits makes it too slow for direct connection to a microprocessor, but the mechanical robustness and low cost of flash makes it ideal for mass storage in mobile devices.</li>
</li>
<li>
<h5 id="I">I</h5>
<p>FAB</p>
<li>Common name for a semiconductor fabrication plant, a factory used to manufacture integrated circuits.</li>
<p>FAN-OUT</p>
<li>Also known as Embedded Wafer-Level Ball Grid Array. A chip packaging scheme in which the package is not created on a silicon wafer, but on an artificial wafer made of molding material (e.g., epoxy). The distance between chips is typically larger than on a silicon wafer. Interconnects are created around the chips and electrical connections are made from the chip pads to the interconnects. Any number of additional interconnects can be created on the package in an arbitrary distance (fan-out design), making this scheme ideal for space-sensitive applications in which the chip area would be insufficient to place the required number of interconnects at a suitable distance.</li>
<p>FDC (FAULT DETECTION AND CLASSIFICATION)</p>
<li>An APC technique that uses process state models to deduce the occurrence and location of a fault condition and diagnose the cause of the fault.</li>
<p>FEOL (FRONT-END OF LINE)</p>
<li>The first portion of integrated circuit fabrication including transistor fabrication. FEOL generally covers everything up to (but not including) the deposition of contacts and metal interconnect layers. The term front end is sometimes used to refer the entire process to completed wafers.</li>
<p>FET (FIELD EFFECT TRANSISTOR)</p>
<li>A type of transistor that relies on an electric field to control the flow of charge carriers in a semiconductor material.</li>
<p>FI (FACTORY INTERFACE)</p>
<li>An ultra-clean enclosure mounted to the front of a semiconductor processing system that transfers wafers to and from the cleanroom environment and the interior of the system.</li>
<p>FIELD</p>
<li>A term used in deposition applications to describe the top surface of a wafer as distinct from the surfaces of circuit features such as trenches and vias that are lower than the top surface.</li>
<p>FINFET</p>
<li>A FinFET is a type of FET in which the conducting channel is surrounded on three sides by a thin silicon "fin" which forms the gate of the transistor. Although technically the term only refers to a design with two gates, the term is often used to describe any multi-gate transistor architecture, regardless of the number of gates.</li>
<p>FLASH MEMORY</p>
<li>A type of non-volatile storage technology that requires no power to retain data, unlike DRAM. The name "flash" comes from the fact that the memory is erased and programmed in large blocks, from hundreds to thousands of bits at a time. This inability to address individual bits makes it too slow for direct connection to a microprocessor, but the mechanical robustness and low cost of flash makes it ideal for mass storage in mobile devices.</li>
</li>
<li>
<h5 id="J">J</h5>
<p>FAB</p>
<li>Common name for a semiconductor fabrication plant, a factory used to manufacture integrated circuits.</li>
<p>FAN-OUT</p>
<li>Also known as Embedded Wafer-Level Ball Grid Array. A chip packaging scheme in which the package is not created on a silicon wafer, but on an artificial wafer made of molding material (e.g., epoxy). The distance between chips is typically larger than on a silicon wafer. Interconnects are created around the chips and electrical connections are made from the chip pads to the interconnects. Any number of additional interconnects can be created on the package in an arbitrary distance (fan-out design), making this scheme ideal for space-sensitive applications in which the chip area would be insufficient to place the required number of interconnects at a suitable distance.</li>
<p>FDC (FAULT DETECTION AND CLASSIFICATION)</p>
<li>An APC technique that uses process state models to deduce the occurrence and location of a fault condition and diagnose the cause of the fault.</li>
<p>FEOL (FRONT-END OF LINE)</p>
<li>The first portion of integrated circuit fabrication including transistor fabrication. FEOL generally covers everything up to (but not including) the deposition of contacts and metal interconnect layers. The term front end is sometimes used to refer the entire process to completed wafers.</li>
<p>FET (FIELD EFFECT TRANSISTOR)</p>
<li>A type of transistor that relies on an electric field to control the flow of charge carriers in a semiconductor material.</li>
<p>FI (FACTORY INTERFACE)</p>
<li>An ultra-clean enclosure mounted to the front of a semiconductor processing system that transfers wafers to and from the cleanroom environment and the interior of the system.</li>
<p>FIELD</p>
<li>A term used in deposition applications to describe the top surface of a wafer as distinct from the surfaces of circuit features such as trenches and vias that are lower than the top surface.</li>
<p>FINFET</p>
<li>A FinFET is a type of FET in which the conducting channel is surrounded on three sides by a thin silicon "fin" which forms the gate of the transistor. Although technically the term only refers to a design with two gates, the term is often used to describe any multi-gate transistor architecture, regardless of the number of gates.</li>
<p>FLASH MEMORY</p>
<li>A type of non-volatile storage technology that requires no power to retain data, unlike DRAM. The name "flash" comes from the fact that the memory is erased and programmed in large blocks, from hundreds to thousands of bits at a time. This inability to address individual bits makes it too slow for direct connection to a microprocessor, but the mechanical robustness and low cost of flash makes it ideal for mass storage in mobile devices.</li>
</li>
<li>
<h5 id="K">K</h5>
<p>FAB</p>
<li>Common name for a semiconductor fabrication plant, a factory used to manufacture integrated circuits.</li>
<p>FAN-OUT</p>
<li>Also known as Embedded Wafer-Level Ball Grid Array. A chip packaging scheme in which the package is not created on a silicon wafer, but on an artificial wafer made of molding material (e.g., epoxy). The distance between chips is typically larger than on a silicon wafer. Interconnects are created around the chips and electrical connections are made from the chip pads to the interconnects. Any number of additional interconnects can be created on the package in an arbitrary distance (fan-out design), making this scheme ideal for space-sensitive applications in which the chip area would be insufficient to place the required number of interconnects at a suitable distance.</li>
<p>FDC (FAULT DETECTION AND CLASSIFICATION)</p>
<li>An APC technique that uses process state models to deduce the occurrence and location of a fault condition and diagnose the cause of the fault.</li>
<p>FEOL (FRONT-END OF LINE)</p>
<li>The first portion of integrated circuit fabrication including transistor fabrication. FEOL generally covers everything up to (but not including) the deposition of contacts and metal interconnect layers. The term front end is sometimes used to refer the entire process to completed wafers.</li>
<p>FET (FIELD EFFECT TRANSISTOR)</p>
<li>A type of transistor that relies on an electric field to control the flow of charge carriers in a semiconductor material.</li>
<p>FI (FACTORY INTERFACE)</p>
<li>An ultra-clean enclosure mounted to the front of a semiconductor processing system that transfers wafers to and from the cleanroom environment and the interior of the system.</li>
<p>FIELD</p>
<li>A term used in deposition applications to describe the top surface of a wafer as distinct from the surfaces of circuit features such as trenches and vias that are lower than the top surface.</li>
<p>FINFET</p>
<li>A FinFET is a type of FET in which the conducting channel is surrounded on three sides by a thin silicon "fin" which forms the gate of the transistor. Although technically the term only refers to a design with two gates, the term is often used to describe any multi-gate transistor architecture, regardless of the number of gates.</li>
<p>FLASH MEMORY</p>
<li>A type of non-volatile storage technology that requires no power to retain data, unlike DRAM. The name "flash" comes from the fact that the memory is erased and programmed in large blocks, from hundreds to thousands of bits at a time. This inability to address individual bits makes it too slow for direct connection to a microprocessor, but the mechanical robustness and low cost of flash makes it ideal for mass storage in mobile devices.</li>
</li>
<li>
<h5 id="L">L</h5>
<p>FAB</p>
<li>Common name for a semiconductor fabrication plant, a factory used to manufacture integrated circuits.</li>
<p>FAN-OUT</p>
<li>Also known as Embedded Wafer-Level Ball Grid Array. A chip packaging scheme in which the package is not created on a silicon wafer, but on an artificial wafer made of molding material (e.g., epoxy). The distance between chips is typically larger than on a silicon wafer. Interconnects are created around the chips and electrical connections are made from the chip pads to the interconnects. Any number of additional interconnects can be created on the package in an arbitrary distance (fan-out design), making this scheme ideal for space-sensitive applications in which the chip area would be insufficient to place the required number of interconnects at a suitable distance.</li>
<p>FDC (FAULT DETECTION AND CLASSIFICATION)</p>
<li>An APC technique that uses process state models to deduce the occurrence and location of a fault condition and diagnose the cause of the fault.</li>
<p>FEOL (FRONT-END OF LINE)</p>
<li>The first portion of integrated circuit fabrication including transistor fabrication. FEOL generally covers everything up to (but not including) the deposition of contacts and metal interconnect layers. The term front end is sometimes used to refer the entire process to completed wafers.</li>
<p>FET (FIELD EFFECT TRANSISTOR)</p>
<li>A type of transistor that relies on an electric field to control the flow of charge carriers in a semiconductor material.</li>
<p>FI (FACTORY INTERFACE)</p>
<li>An ultra-clean enclosure mounted to the front of a semiconductor processing system that transfers wafers to and from the cleanroom environment and the interior of the system.</li>
<p>FIELD</p>
<li>A term used in deposition applications to describe the top surface of a wafer as distinct from the surfaces of circuit features such as trenches and vias that are lower than the top surface.</li>
<p>FINFET</p>
<li>A FinFET is a type of FET in which the conducting channel is surrounded on three sides by a thin silicon "fin" which forms the gate of the transistor. Although technically the term only refers to a design with two gates, the term is often used to describe any multi-gate transistor architecture, regardless of the number of gates.</li>
<p>FLASH MEMORY</p>
<li>A type of non-volatile storage technology that requires no power to retain data, unlike DRAM. The name "flash" comes from the fact that the memory is erased and programmed in large blocks, from hundreds to thousands of bits at a time. This inability to address individual bits makes it too slow for direct connection to a microprocessor, but the mechanical robustness and low cost of flash makes it ideal for mass storage in mobile devices.</li>
</li>
<li>
<h5 id="M">M</h5>
<p>FAB</p>
<li>Common name for a semiconductor fabrication plant, a factory used to manufacture integrated circuits.</li>
<p>FAN-OUT</p>
<li>Also known as Embedded Wafer-Level Ball Grid Array. A chip packaging scheme in which the package is not created on a silicon wafer, but on an artificial wafer made of molding material (e.g., epoxy). The distance between chips is typically larger than on a silicon wafer. Interconnects are created around the chips and electrical connections are made from the chip pads to the interconnects. Any number of additional interconnects can be created on the package in an arbitrary distance (fan-out design), making this scheme ideal for space-sensitive applications in which the chip area would be insufficient to place the required number of interconnects at a suitable distance.</li>
<p>FDC (FAULT DETECTION AND CLASSIFICATION)</p>
<li>An APC technique that uses process state models to deduce the occurrence and location of a fault condition and diagnose the cause of the fault.</li>
<p>FEOL (FRONT-END OF LINE)</p>
<li>The first portion of integrated circuit fabrication including transistor fabrication. FEOL generally covers everything up to (but not including) the deposition of contacts and metal interconnect layers. The term front end is sometimes used to refer the entire process to completed wafers.</li>
<p>FET (FIELD EFFECT TRANSISTOR)</p>
<li>A type of transistor that relies on an electric field to control the flow of charge carriers in a semiconductor material.</li>
<p>FI (FACTORY INTERFACE)</p>
<li>An ultra-clean enclosure mounted to the front of a semiconductor processing system that transfers wafers to and from the cleanroom environment and the interior of the system.</li>
<p>FIELD</p>
<li>A term used in deposition applications to describe the top surface of a wafer as distinct from the surfaces of circuit features such as trenches and vias that are lower than the top surface.</li>
<p>FINFET</p>
<li>A FinFET is a type of FET in which the conducting channel is surrounded on three sides by a thin silicon "fin" which forms the gate of the transistor. Although technically the term only refers to a design with two gates, the term is often used to describe any multi-gate transistor architecture, regardless of the number of gates.</li>
<p>FLASH MEMORY</p>
<li>A type of non-volatile storage technology that requires no power to retain data, unlike DRAM. The name "flash" comes from the fact that the memory is erased and programmed in large blocks, from hundreds to thousands of bits at a time. This inability to address individual bits makes it too slow for direct connection to a microprocessor, but the mechanical robustness and low cost of flash makes it ideal for mass storage in mobile devices.</li>
</li>
<li>
<h5 id="N">N</h5>
<p>FAB</p>
<li>Common name for a semiconductor fabrication plant, a factory used to manufacture integrated circuits.</li>
<p>FAN-OUT</p>
<li>Also known as Embedded Wafer-Level Ball Grid Array. A chip packaging scheme in which the package is not created on a silicon wafer, but on an artificial wafer made of molding material (e.g., epoxy). The distance between chips is typically larger than on a silicon wafer. Interconnects are created around the chips and electrical connections are made from the chip pads to the interconnects. Any number of additional interconnects can be created on the package in an arbitrary distance (fan-out design), making this scheme ideal for space-sensitive applications in which the chip area would be insufficient to place the required number of interconnects at a suitable distance.</li>
<p>FDC (FAULT DETECTION AND CLASSIFICATION)</p>
<li>An APC technique that uses process state models to deduce the occurrence and location of a fault condition and diagnose the cause of the fault.</li>
<p>FEOL (FRONT-END OF LINE)</p>
<li>The first portion of integrated circuit fabrication including transistor fabrication. FEOL generally covers everything up to (but not including) the deposition of contacts and metal interconnect layers. The term front end is sometimes used to refer the entire process to completed wafers.</li>
<p>FET (FIELD EFFECT TRANSISTOR)</p>
<li>A type of transistor that relies on an electric field to control the flow of charge carriers in a semiconductor material.</li>
<p>FI (FACTORY INTERFACE)</p>
<li>An ultra-clean enclosure mounted to the front of a semiconductor processing system that transfers wafers to and from the cleanroom environment and the interior of the system.</li>
<p>FIELD</p>
<li>A term used in deposition applications to describe the top surface of a wafer as distinct from the surfaces of circuit features such as trenches and vias that are lower than the top surface.</li>
<p>FINFET</p>
<li>A FinFET is a type of FET in which the conducting channel is surrounded on three sides by a thin silicon "fin" which forms the gate of the transistor. Although technically the term only refers to a design with two gates, the term is often used to describe any multi-gate transistor architecture, regardless of the number of gates.</li>
<p>FLASH MEMORY</p>
<li>A type of non-volatile storage technology that requires no power to retain data, unlike DRAM. The name "flash" comes from the fact that the memory is erased and programmed in large blocks, from hundreds to thousands of bits at a time. This inability to address individual bits makes it too slow for direct connection to a microprocessor, but the mechanical robustness and low cost of flash makes it ideal for mass storage in mobile devices.</li>
</li>
<li>
<h5 id="O">O</h5>
<p>FAB</p>
<li>Common name for a semiconductor fabrication plant, a factory used to manufacture integrated circuits.</li>
<p>FAN-OUT</p>
<li>Also known as Embedded Wafer-Level Ball Grid Array. A chip packaging scheme in which the package is not created on a silicon wafer, but on an artificial wafer made of molding material (e.g., epoxy). The distance between chips is typically larger than on a silicon wafer. Interconnects are created around the chips and electrical connections are made from the chip pads to the interconnects. Any number of additional interconnects can be created on the package in an arbitrary distance (fan-out design), making this scheme ideal for space-sensitive applications in which the chip area would be insufficient to place the required number of interconnects at a suitable distance.</li>
<p>FDC (FAULT DETECTION AND CLASSIFICATION)</p>
<li>An APC technique that uses process state models to deduce the occurrence and location of a fault condition and diagnose the cause of the fault.</li>
<p>FEOL (FRONT-END OF LINE)</p>
<li>The first portion of integrated circuit fabrication including transistor fabrication. FEOL generally covers everything up to (but not including) the deposition of contacts and metal interconnect layers. The term front end is sometimes used to refer the entire process to completed wafers.</li>
<p>FET (FIELD EFFECT TRANSISTOR)</p>
<li>A type of transistor that relies on an electric field to control the flow of charge carriers in a semiconductor material.</li>
<p>FI (FACTORY INTERFACE)</p>
<li>An ultra-clean enclosure mounted to the front of a semiconductor processing system that transfers wafers to and from the cleanroom environment and the interior of the system.</li>
<p>FIELD</p>
<li>A term used in deposition applications to describe the top surface of a wafer as distinct from the surfaces of circuit features such as trenches and vias that are lower than the top surface.</li>
<p>FINFET</p>
<li>A FinFET is a type of FET in which the conducting channel is surrounded on three sides by a thin silicon "fin" which forms the gate of the transistor. Although technically the term only refers to a design with two gates, the term is often used to describe any multi-gate transistor architecture, regardless of the number of gates.</li>
<p>FLASH MEMORY</p>
<li>A type of non-volatile storage technology that requires no power to retain data, unlike DRAM. The name "flash" comes from the fact that the memory is erased and programmed in large blocks, from hundreds to thousands of bits at a time. This inability to address individual bits makes it too slow for direct connection to a microprocessor, but the mechanical robustness and low cost of flash makes it ideal for mass storage in mobile devices.</li>
</li>
<li>
<h5 id="P">P</h5>
<p>FAB</p>
<li>Common name for a semiconductor fabrication plant, a factory used to manufacture integrated circuits.</li>
<p>FAN-OUT</p>
<li>Also known as Embedded Wafer-Level Ball Grid Array. A chip packaging scheme in which the package is not created on a silicon wafer, but on an artificial wafer made of molding material (e.g., epoxy). The distance between chips is typically larger than on a silicon wafer. Interconnects are created around the chips and electrical connections are made from the chip pads to the interconnects. Any number of additional interconnects can be created on the package in an arbitrary distance (fan-out design), making this scheme ideal for space-sensitive applications in which the chip area would be insufficient to place the required number of interconnects at a suitable distance.</li>
<p>FDC (FAULT DETECTION AND CLASSIFICATION)</p>
<li>An APC technique that uses process state models to deduce the occurrence and location of a fault condition and diagnose the cause of the fault.</li>
<p>FEOL (FRONT-END OF LINE)</p>
<li>The first portion of integrated circuit fabrication including transistor fabrication. FEOL generally covers everything up to (but not including) the deposition of contacts and metal interconnect layers. The term front end is sometimes used to refer the entire process to completed wafers.</li>
<p>FET (FIELD EFFECT TRANSISTOR)</p>
<li>A type of transistor that relies on an electric field to control the flow of charge carriers in a semiconductor material.</li>
<p>FI (FACTORY INTERFACE)</p>
<li>An ultra-clean enclosure mounted to the front of a semiconductor processing system that transfers wafers to and from the cleanroom environment and the interior of the system.</li>
<p>FIELD</p>
<li>A term used in deposition applications to describe the top surface of a wafer as distinct from the surfaces of circuit features such as trenches and vias that are lower than the top surface.</li>
<p>FINFET</p>
<li>A FinFET is a type of FET in which the conducting channel is surrounded on three sides by a thin silicon "fin" which forms the gate of the transistor. Although technically the term only refers to a design with two gates, the term is often used to describe any multi-gate transistor architecture, regardless of the number of gates.</li>
<p>FLASH MEMORY</p>
<li>A type of non-volatile storage technology that requires no power to retain data, unlike DRAM. The name "flash" comes from the fact that the memory is erased and programmed in large blocks, from hundreds to thousands of bits at a time. This inability to address individual bits makes it too slow for direct connection to a microprocessor, but the mechanical robustness and low cost of flash makes it ideal for mass storage in mobile devices.</li>
</li>
<li>
<h5 id="Q">Q</h5>
<p>FAB</p>
<li>Common name for a semiconductor fabrication plant, a factory used to manufacture integrated circuits.</li>
<p>FAN-OUT</p>
<li>Also known as Embedded Wafer-Level Ball Grid Array. A chip packaging scheme in which the package is not created on a silicon wafer, but on an artificial wafer made of molding material (e.g., epoxy). The distance between chips is typically larger than on a silicon wafer. Interconnects are created around the chips and electrical connections are made from the chip pads to the interconnects. Any number of additional interconnects can be created on the package in an arbitrary distance (fan-out design), making this scheme ideal for space-sensitive applications in which the chip area would be insufficient to place the required number of interconnects at a suitable distance.</li>
<p>FDC (FAULT DETECTION AND CLASSIFICATION)</p>
<li>An APC technique that uses process state models to deduce the occurrence and location of a fault condition and diagnose the cause of the fault.</li>
<p>FEOL (FRONT-END OF LINE)</p>
<li>The first portion of integrated circuit fabrication including transistor fabrication. FEOL generally covers everything up to (but not including) the deposition of contacts and metal interconnect layers. The term front end is sometimes used to refer the entire process to completed wafers.</li>
<p>FET (FIELD EFFECT TRANSISTOR)</p>
<li>A type of transistor that relies on an electric field to control the flow of charge carriers in a semiconductor material.</li>
<p>FI (FACTORY INTERFACE)</p>
<li>An ultra-clean enclosure mounted to the front of a semiconductor processing system that transfers wafers to and from the cleanroom environment and the interior of the system.</li>
<p>FIELD</p>
<li>A term used in deposition applications to describe the top surface of a wafer as distinct from the surfaces of circuit features such as trenches and vias that are lower than the top surface.</li>
<p>FINFET</p>
<li>A FinFET is a type of FET in which the conducting channel is surrounded on three sides by a thin silicon "fin" which forms the gate of the transistor. Although technically the term only refers to a design with two gates, the term is often used to describe any multi-gate transistor architecture, regardless of the number of gates.</li>
<p>FLASH MEMORY</p>
<li>A type of non-volatile storage technology that requires no power to retain data, unlike DRAM. The name "flash" comes from the fact that the memory is erased and programmed in large blocks, from hundreds to thousands of bits at a time. This inability to address individual bits makes it too slow for direct connection to a microprocessor, but the mechanical robustness and low cost of flash makes it ideal for mass storage in mobile devices.</li>
</li>
<li>
<h5 id="R">R</h5>
<p>FAB</p>
<li>Common name for a semiconductor fabrication plant, a factory used to manufacture integrated circuits.</li>
<p>FAN-OUT</p>
<li>Also known as Embedded Wafer-Level Ball Grid Array. A chip packaging scheme in which the package is not created on a silicon wafer, but on an artificial wafer made of molding material (e.g., epoxy). The distance between chips is typically larger than on a silicon wafer. Interconnects are created around the chips and electrical connections are made from the chip pads to the interconnects. Any number of additional interconnects can be created on the package in an arbitrary distance (fan-out design), making this scheme ideal for space-sensitive applications in which the chip area would be insufficient to place the required number of interconnects at a suitable distance.</li>
<p>FDC (FAULT DETECTION AND CLASSIFICATION)</p>
<li>An APC technique that uses process state models to deduce the occurrence and location of a fault condition and diagnose the cause of the fault.</li>
<p>FEOL (FRONT-END OF LINE)</p>
<li>The first portion of integrated circuit fabrication including transistor fabrication. FEOL generally covers everything up to (but not including) the deposition of contacts and metal interconnect layers. The term front end is sometimes used to refer the entire process to completed wafers.</li>
<p>FET (FIELD EFFECT TRANSISTOR)</p>
<li>A type of transistor that relies on an electric field to control the flow of charge carriers in a semiconductor material.</li>
<p>FI (FACTORY INTERFACE)</p>
<li>An ultra-clean enclosure mounted to the front of a semiconductor processing system that transfers wafers to and from the cleanroom environment and the interior of the system.</li>
<p>FIELD</p>
<li>A term used in deposition applications to describe the top surface of a wafer as distinct from the surfaces of circuit features such as trenches and vias that are lower than the top surface.</li>
<p>FINFET</p>
<li>A FinFET is a type of FET in which the conducting channel is surrounded on three sides by a thin silicon "fin" which forms the gate of the transistor. Although technically the term only refers to a design with two gates, the term is often used to describe any multi-gate transistor architecture, regardless of the number of gates.</li>
<p>FLASH MEMORY</p>
<li>A type of non-volatile storage technology that requires no power to retain data, unlike DRAM. The name "flash" comes from the fact that the memory is erased and programmed in large blocks, from hundreds to thousands of bits at a time. This inability to address individual bits makes it too slow for direct connection to a microprocessor, but the mechanical robustness and low cost of flash makes it ideal for mass storage in mobile devices.</li>
</li> -->
<!-- <li>
<h5 id="S">S</h5>
<p>FAB</p>
<li>Common name for a semiconductor fabrication plant, a factory used to manufacture integrated circuits.</li>
<p>FAN-OUT</p>
<li>Also known as Embedded Wafer-Level Ball Grid Array. A chip packaging scheme in which the package is not created on a silicon wafer, but on an artificial wafer made of molding material (e.g., epoxy). The distance between chips is typically larger than on a silicon wafer. Interconnects are created around the chips and electrical connections are made from the chip pads to the interconnects. Any number of additional interconnects can be created on the package in an arbitrary distance (fan-out design), making this scheme ideal for space-sensitive applications in which the chip area would be insufficient to place the required number of interconnects at a suitable distance.</li>
<p>FDC (FAULT DETECTION AND CLASSIFICATION)</p>
<li>An APC technique that uses process state models to deduce the occurrence and location of a fault condition and diagnose the cause of the fault.</li>
<p>FEOL (FRONT-END OF LINE)</p>
<li>The first portion of integrated circuit fabrication including transistor fabrication. FEOL generally covers everything up to (but not including) the deposition of contacts and metal interconnect layers. The term front end is sometimes used to refer the entire process to completed wafers.</li>
<p>FET (FIELD EFFECT TRANSISTOR)</p>
<li>A type of transistor that relies on an electric field to control the flow of charge carriers in a semiconductor material.</li>
<p>FI (FACTORY INTERFACE)</p>
<li>An ultra-clean enclosure mounted to the front of a semiconductor processing system that transfers wafers to and from the cleanroom environment and the interior of the system.</li>
<p>FIELD</p>
<li>A term used in deposition applications to describe the top surface of a wafer as distinct from the surfaces of circuit features such as trenches and vias that are lower than the top surface.</li>
<p>FINFET</p>
<li>A FinFET is a type of FET in which the conducting channel is surrounded on three sides by a thin silicon "fin" which forms the gate of the transistor. Although technically the term only refers to a design with two gates, the term is often used to describe any multi-gate transistor architecture, regardless of the number of gates.</li>
<p>FLASH MEMORY</p>
<li>A type of non-volatile storage technology that requires no power to retain data, unlike DRAM. The name "flash" comes from the fact that the memory is erased and programmed in large blocks, from hundreds to thousands of bits at a time. This inability to address individual bits makes it too slow for direct connection to a microprocessor, but the mechanical robustness and low cost of flash makes it ideal for mass storage in mobile devices.</li>
</li> -->
<!-- <li>
<h5 id="T">T</h5>
<p>FAB</p>
<li>Common name for a semiconductor fabrication plant, a factory used to manufacture integrated circuits.</li>
<p>FAN-OUT</p>
<li>Also known as Embedded Wafer-Level Ball Grid Array. A chip packaging scheme in which the package is not created on a silicon wafer, but on an artificial wafer made of molding material (e.g., epoxy). The distance between chips is typically larger than on a silicon wafer. Interconnects are created around the chips and electrical connections are made from the chip pads to the interconnects. Any number of additional interconnects can be created on the package in an arbitrary distance (fan-out design), making this scheme ideal for space-sensitive applications in which the chip area would be insufficient to place the required number of interconnects at a suitable distance.</li>
<p>FDC (FAULT DETECTION AND CLASSIFICATION)</p>
<li>An APC technique that uses process state models to deduce the occurrence and location of a fault condition and diagnose the cause of the fault.</li>
<p>FEOL (FRONT-END OF LINE)</p>
<li>The first portion of integrated circuit fabrication including transistor fabrication. FEOL generally covers everything up to (but not including) the deposition of contacts and metal interconnect layers. The term front end is sometimes used to refer the entire process to completed wafers.</li>
<p>FET (FIELD EFFECT TRANSISTOR)</p>
<li>A type of transistor that relies on an electric field to control the flow of charge carriers in a semiconductor material.</li>
<p>FI (FACTORY INTERFACE)</p>
<li>An ultra-clean enclosure mounted to the front of a semiconductor processing system that transfers wafers to and from the cleanroom environment and the interior of the system.</li>
<p>FIELD</p>
<li>A term used in deposition applications to describe the top surface of a wafer as distinct from the surfaces of circuit features such as trenches and vias that are lower than the top surface.</li>
<p>FINFET</p>
<li>A FinFET is a type of FET in which the conducting channel is surrounded on three sides by a thin silicon "fin" which forms the gate of the transistor. Although technically the term only refers to a design with two gates, the term is often used to describe any multi-gate transistor architecture, regardless of the number of gates.</li>
<p>FLASH MEMORY</p>
<li>A type of non-volatile storage technology that requires no power to retain data, unlike DRAM. The name "flash" comes from the fact that the memory is erased and programmed in large blocks, from hundreds to thousands of bits at a time. This inability to address individual bits makes it too slow for direct connection to a microprocessor, but the mechanical robustness and low cost of flash makes it ideal for mass storage in mobile devices.</li>
</li> -->
<!--
<li>
<h5 id="U">U</h5>
<p>FAB</p>
<li>Common name for a semiconductor fabrication plant, a factory used to manufacture integrated circuits.</li>
<p>FAN-OUT</p>
<li>Also known as Embedded Wafer-Level Ball Grid Array. A chip packaging scheme in which the package is not created on a silicon wafer, but on an artificial wafer made of molding material (e.g., epoxy). The distance between chips is typically larger than on a silicon wafer. Interconnects are created around the chips and electrical connections are made from the chip pads to the interconnects. Any number of additional interconnects can be created on the package in an arbitrary distance (fan-out design), making this scheme ideal for space-sensitive applications in which the chip area would be insufficient to place the required number of interconnects at a suitable distance.</li>
<p>FDC (FAULT DETECTION AND CLASSIFICATION)</p>
<li>An APC technique that uses process state models to deduce the occurrence and location of a fault condition and diagnose the cause of the fault.</li>
<p>FEOL (FRONT-END OF LINE)</p>
<li>The first portion of integrated circuit fabrication including transistor fabrication. FEOL generally covers everything up to (but not including) the deposition of contacts and metal interconnect layers. The term front end is sometimes used to refer the entire process to completed wafers.</li>
<p>FET (FIELD EFFECT TRANSISTOR)</p>
<li>A type of transistor that relies on an electric field to control the flow of charge carriers in a semiconductor material.</li>
<p>FI (FACTORY INTERFACE)</p>
<li>An ultra-clean enclosure mounted to the front of a semiconductor processing system that transfers wafers to and from the cleanroom environment and the interior of the system.</li>
<p>FIELD</p>
<li>A term used in deposition applications to describe the top surface of a wafer as distinct from the surfaces of circuit features such as trenches and vias that are lower than the top surface.</li>
<p>FINFET</p>
<li>A FinFET is a type of FET in which the conducting channel is surrounded on three sides by a thin silicon "fin" which forms the gate of the transistor. Although technically the term only refers to a design with two gates, the term is often used to describe any multi-gate transistor architecture, regardless of the number of gates.</li>
<p>FLASH MEMORY</p>
<li>A type of non-volatile storage technology that requires no power to retain data, unlike DRAM. The name "flash" comes from the fact that the memory is erased and programmed in large blocks, from hundreds to thousands of bits at a time. This inability to address individual bits makes it too slow for direct connection to a microprocessor, but the mechanical robustness and low cost of flash makes it ideal for mass storage in mobile devices.</li>
</li> -->
<!-- <li>
<h5 id="V">V</h5>
<p>FAB</p>
<li>Common name for a semiconductor fabrication plant, a factory used to manufacture integrated circuits.</li>
<p>FAN-OUT</p>
<li>Also known as Embedded Wafer-Level Ball Grid Array. A chip packaging scheme in which the package is not created on a silicon wafer, but on an artificial wafer made of molding material (e.g., epoxy). The distance between chips is typically larger than on a silicon wafer. Interconnects are created around the chips and electrical connections are made from the chip pads to the interconnects. Any number of additional interconnects can be created on the package in an arbitrary distance (fan-out design), making this scheme ideal for space-sensitive applications in which the chip area would be insufficient to place the required number of interconnects at a suitable distance.</li>
<p>FDC (FAULT DETECTION AND CLASSIFICATION)</p>
<li>An APC technique that uses process state models to deduce the occurrence and location of a fault condition and diagnose the cause of the fault.</li>
<p>FEOL (FRONT-END OF LINE)</p>
<li>The first portion of integrated circuit fabrication including transistor fabrication. FEOL generally covers everything up to (but not including) the deposition of contacts and metal interconnect layers. The term front end is sometimes used to refer the entire process to completed wafers.</li>
<p>FET (FIELD EFFECT TRANSISTOR)</p>
<li>A type of transistor that relies on an electric field to control the flow of charge carriers in a semiconductor material.</li>
<p>FI (FACTORY INTERFACE)</p>
<li>An ultra-clean enclosure mounted to the front of a semiconductor processing system that transfers wafers to and from the cleanroom environment and the interior of the system.</li>
<p>FIELD</p>
<li>A term used in deposition applications to describe the top surface of a wafer as distinct from the surfaces of circuit features such as trenches and vias that are lower than the top surface.</li>
<p>FINFET</p>
<li>A FinFET is a type of FET in which the conducting channel is surrounded on three sides by a thin silicon "fin" which forms the gate of the transistor. Although technically the term only refers to a design with two gates, the term is often used to describe any multi-gate transistor architecture, regardless of the number of gates.</li>
<p>FLASH MEMORY</p>
<li>A type of non-volatile storage technology that requires no power to retain data, unlike DRAM. The name "flash" comes from the fact that the memory is erased and programmed in large blocks, from hundreds to thousands of bits at a time. This inability to address individual bits makes it too slow for direct connection to a microprocessor, but the mechanical robustness and low cost of flash makes it ideal for mass storage in mobile devices.</li>
</li> -->
<!-- <li>
<h5 id="W">W</h5>
<p>FAB</p>
<li>Common name for a semiconductor fabrication plant, a factory used to manufacture integrated circuits.</li>
<p>FAN-OUT</p>
<li>Also known as Embedded Wafer-Level Ball Grid Array. A chip packaging scheme in which the package is not created on a silicon wafer, but on an artificial wafer made of molding material (e.g., epoxy). The distance between chips is typically larger than on a silicon wafer. Interconnects are created around the chips and electrical connections are made from the chip pads to the interconnects. Any number of additional interconnects can be created on the package in an arbitrary distance (fan-out design), making this scheme ideal for space-sensitive applications in which the chip area would be insufficient to place the required number of interconnects at a suitable distance.</li>
<p>FDC (FAULT DETECTION AND CLASSIFICATION)</p>
<li>An APC technique that uses process state models to deduce the occurrence and location of a fault condition and diagnose the cause of the fault.</li>
<p>FEOL (FRONT-END OF LINE)</p>
<li>The first portion of integrated circuit fabrication including transistor fabrication. FEOL generally covers everything up to (but not including) the deposition of contacts and metal interconnect layers. The term front end is sometimes used to refer the entire process to completed wafers.</li>
<p>FET (FIELD EFFECT TRANSISTOR)</p>
<li>A type of transistor that relies on an electric field to control the flow of charge carriers in a semiconductor material.</li>
<p>FI (FACTORY INTERFACE)</p>
<li>An ultra-clean enclosure mounted to the front of a semiconductor processing system that transfers wafers to and from the cleanroom environment and the interior of the system.</li>
<p>FIELD</p>
<li>A term used in deposition applications to describe the top surface of a wafer as distinct from the surfaces of circuit features such as trenches and vias that are lower than the top surface.</li>
<p>FINFET</p>
<li>A FinFET is a type of FET in which the conducting channel is surrounded on three sides by a thin silicon "fin" which forms the gate of the transistor. Although technically the term only refers to a design with two gates, the term is often used to describe any multi-gate transistor architecture, regardless of the number of gates.</li>
<p>FLASH MEMORY</p>
<li>A type of non-volatile storage technology that requires no power to retain data, unlike DRAM. The name "flash" comes from the fact that the memory is erased and programmed in large blocks, from hundreds to thousands of bits at a time. This inability to address individual bits makes it too slow for direct connection to a microprocessor, but the mechanical robustness and low cost of flash makes it ideal for mass storage in mobile devices.</li>
</li> -->
<!-- <li>
<h5 id="X">X</h5>
<p>FAB</p>
<li>Common name for a semiconductor fabrication plant, a factory used to manufacture integrated circuits.</li>
<p>FAN-OUT</p>
<li>Also known as Embedded Wafer-Level Ball Grid Array. A chip packaging scheme in which the package is not created on a silicon wafer, but on an artificial wafer made of molding material (e.g., epoxy). The distance between chips is typically larger than on a silicon wafer. Interconnects are created around the chips and electrical connections are made from the chip pads to the interconnects. Any number of additional interconnects can be created on the package in an arbitrary distance (fan-out design), making this scheme ideal for space-sensitive applications in which the chip area would be insufficient to place the required number of interconnects at a suitable distance.</li>
<p>FDC (FAULT DETECTION AND CLASSIFICATION)</p>
<li>An APC technique that uses process state models to deduce the occurrence and location of a fault condition and diagnose the cause of the fault.</li>
<p>FEOL (FRONT-END OF LINE)</p>
<li>The first portion of integrated circuit fabrication including transistor fabrication. FEOL generally covers everything up to (but not including) the deposition of contacts and metal interconnect layers. The term front end is sometimes used to refer the entire process to completed wafers.</li>
<p>FET (FIELD EFFECT TRANSISTOR)</p>
<li>A type of transistor that relies on an electric field to control the flow of charge carriers in a semiconductor material.</li>
<p>FI (FACTORY INTERFACE)</p>
<li>An ultra-clean enclosure mounted to the front of a semiconductor processing system that transfers wafers to and from the cleanroom environment and the interior of the system.</li>
<p>FIELD</p>
<li>A term used in deposition applications to describe the top surface of a wafer as distinct from the surfaces of circuit features such as trenches and vias that are lower than the top surface.</li>
<p>FINFET</p>
<li>A FinFET is a type of FET in which the conducting channel is surrounded on three sides by a thin silicon "fin" which forms the gate of the transistor. Although technically the term only refers to a design with two gates, the term is often used to describe any multi-gate transistor architecture, regardless of the number of gates.</li>
<p>FLASH MEMORY</p>
<li>A type of non-volatile storage technology that requires no power to retain data, unlike DRAM. The name "flash" comes from the fact that the memory is erased and programmed in large blocks, from hundreds to thousands of bits at a time. This inability to address individual bits makes it too slow for direct connection to a microprocessor, but the mechanical robustness and low cost of flash makes it ideal for mass storage in mobile devices.</li>
</li> -->
<!--
<li>
<h5 id="Y">Y</h5>
<p>FAB</p>
<li>Common name for a semiconductor fabrication plant, a factory used to manufacture integrated circuits.</li>
<p>FAN-OUT</p>
<li>Also known as Embedded Wafer-Level Ball Grid Array. A chip packaging scheme in which the package is not created on a silicon wafer, but on an artificial wafer made of molding material (e.g., epoxy). The distance between chips is typically larger than on a silicon wafer. Interconnects are created around the chips and electrical connections are made from the chip pads to the interconnects. Any number of additional interconnects can be created on the package in an arbitrary distance (fan-out design), making this scheme ideal for space-sensitive applications in which the chip area would be insufficient to place the required number of interconnects at a suitable distance.</li>
<p>FDC (FAULT DETECTION AND CLASSIFICATION)</p>
<li>An APC technique that uses process state models to deduce the occurrence and location of a fault condition and diagnose the cause of the fault.</li>
<p>FEOL (FRONT-END OF LINE)</p>
<li>The first portion of integrated circuit fabrication including transistor fabrication. FEOL generally covers everything up to (but not including) the deposition of contacts and metal interconnect layers. The term front end is sometimes used to refer the entire process to completed wafers.</li>
<p>FET (FIELD EFFECT TRANSISTOR)</p>
<li>A type of transistor that relies on an electric field to control the flow of charge carriers in a semiconductor material.</li>
<p>FI (FACTORY INTERFACE)</p>
<li>An ultra-clean enclosure mounted to the front of a semiconductor processing system that transfers wafers to and from the cleanroom environment and the interior of the system.</li>
<p>FIELD</p>
<li>A term used in deposition applications to describe the top surface of a wafer as distinct from the surfaces of circuit features such as trenches and vias that are lower than the top surface.</li>
<p>FINFET</p>
<li>A FinFET is a type of FET in which the conducting channel is surrounded on three sides by a thin silicon "fin" which forms the gate of the transistor. Although technically the term only refers to a design with two gates, the term is often used to describe any multi-gate transistor architecture, regardless of the number of gates.</li>
<p>FLASH MEMORY</p>
<li>A type of non-volatile storage technology that requires no power to retain data, unlike DRAM. The name "flash" comes from the fact that the memory is erased and programmed in large blocks, from hundreds to thousands of bits at a time. This inability to address individual bits makes it too slow for direct connection to a microprocessor, but the mechanical robustness and low cost of flash makes it ideal for mass storage in mobile devices.</li>
</li> -->
<!--
<li>
<h5 id="Z">Z</h5>
<p>FAB</p>
<li>Common name for a semiconductor fabrication plant, a factory used to manufacture integrated circuits.</li>
<p>FAN-OUT</p>
<li>Also known as Embedded Wafer-Level Ball Grid Array. A chip packaging scheme in which the package is not created on a silicon wafer, but on an artificial wafer made of molding material (e.g., epoxy). The distance between chips is typically larger than on a silicon wafer. Interconnects are created around the chips and electrical connections are made from the chip pads to the interconnects. Any number of additional interconnects can be created on the package in an arbitrary distance (fan-out design), making this scheme ideal for space-sensitive applications in which the chip area would be insufficient to place the required number of interconnects at a suitable distance.</li>
<p>FDC (FAULT DETECTION AND CLASSIFICATION)</p>
<li>An APC technique that uses process state models to deduce the occurrence and location of a fault condition and diagnose the cause of the fault.</li>
<p>FEOL (FRONT-END OF LINE)</p>
<li>The first portion of integrated circuit fabrication including transistor fabrication. FEOL generally covers everything up to (but not including) the deposition of contacts and metal interconnect layers. The term front end is sometimes used to refer the entire process to completed wafers.</li>
<p>FET (FIELD EFFECT TRANSISTOR)</p>
<li>A type of transistor that relies on an electric field to control the flow of charge carriers in a semiconductor material.</li>
<p>FI (FACTORY INTERFACE)</p>
<li>An ultra-clean enclosure mounted to the front of a semiconductor processing system that transfers wafers to and from the cleanroom environment and the interior of the system.</li>
<p>FIELD</p>
<li>A term used in deposition applications to describe the top surface of a wafer as distinct from the surfaces of circuit features such as trenches and vias that are lower than the top surface.</li>
<p>FINFET</p>
<li>A FinFET is a type of FET in which the conducting channel is surrounded on three sides by a thin silicon "fin" which forms the gate of the transistor. Although technically the term only refers to a design with two gates, the term is often used to describe any multi-gate transistor architecture, regardless of the number of gates.</li>
<p>FLASH MEMORY</p>
<li>A type of non-volatile storage technology that requires no power to retain data, unlike DRAM. The name "flash" comes from the fact that the memory is erased and programmed in large blocks, from hundreds to thousands of bits at a time. This inability to address individual bits makes it too slow for direct connection to a microprocessor, but the mechanical robustness and low cost of flash makes it ideal for mass storage in mobile devices.</li>
</li> -->
</ul>
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